As semiconductor devices become more and more dense, it has become necessary to maximize the amount of die space used in order to successfully manufacture these devices while retaining relatively small package sizes. This is particularly true with dynamic random access memories (DRAMs) as memory density has increased while the space allowed for each storage capacitor has decreased.
FIG. 1, demonstrates a conventional approach taken to form a storage capacitor for DRAMs in less space. In this example, a bottom storage capacitor electrode 12 made from conductively doped polysilicon connects to diffusion layer 11. Electrode 12 was subjected to a rapid thermal processing step (in this case rapid thermal nitride (RTN)) which converts a top portion of polysilicon 12 into silicon nitride layer 13 (or RTN layer 13). Capacitor cell dielectric 14, tantalum oxide (Ta.sub.2 O.sub.5), was formed over RTN layer 13. Finally, a titanium nitride (TiN) layer 15 was formed over cell dielectric layer 13 to form a top storage capacitor electrode.
A main problem with this approach is the fact that top electrode 15 will react chemically with cell dielectric 14 and thereby degrade the dielectric constant of the cell dielectric. This reaction will lead to a leaky capacitor as stored charge will propagate through leaky dielectric 15 and thus degrade the capacitor's ability to retain charge.
To solve the above problem, the present invention teaches a method to sufficiently eliminate the chemically degradation between a conductor and an insulator by forming a barrier therebetween.